2 research outputs found
Energy reconstruction on the LHC ATLAS TileCal upgraded front end: feasibility study for a sROD co-processing unit
Dissertation presented in ful lment of the requirements for the degree of:
Master of Science in Physics
2016The Phase-II upgrade of the Large Hadron Collider at CERN in the early 2020s
will enable an order of magnitude increase in the data produced, unlocking the
potential for new physics discoveries. In the ATLAS detector, the upgraded Hadronic
Tile Calorimeter (TileCal) Phase-II front end read out system is currently being
prototyped to handle a total data throughput of 5.1 TB/s, from the current 20.4 GB/s.
The FPGA based Super Read Out Driver (sROD) prototype must perform an energy
reconstruction algorithm on 2.88 GB/s raw data, or 275 million events per second.
Due to the very high level of pro ciency required and time consuming nature of
FPGA rmware development, it may be more e ective to implement certain complex
energy reconstruction and monitoring algorithms on a general purpose, CPU based
sROD co-processor. Hence, the feasibility of a general purpose ARM System on Chip
based co-processing unit (PU) for the sROD is determined in this work.
A PCI-Express test platform was designed and constructed to link two ARM
Cortex-A9 SoCs via their PCI-Express Gen-2 x1 interfaces. Test results indicate that
the latency of the PCI-Express interface is su ciently low and the data throughput is
superior to that of alternative interfaces such as Ethernet, for use as an interconnect
for the SoCs to the sROD. CPU performance benchmarks were performed on ve ARM
development platforms to determine the CPU integer,
oating point and memory
system performance as well as energy e ciency. To complement the benchmarks,
Fast Fourier Transform and Optimal Filtering (OF) applications were also tested.
Based on the test results, in order for the PU to process 275 million events per
second with OF, within the 6 s timing budget of the ATLAS triggering system, a
cluster of three Tegra-K1, Cortex-A15 SoCs connected to the sROD via a Gen-2 x8
PCI-Express interface would be suitable. A high level design for the PU is proposed
which surpasses the requirements for the sROD co-processor and can also be used
in a general purpose, high data throughput system, with 80 Gb/s Ethernet and
15 GB/s PCI-Express throughput, using four X-Gene SoCs
The Development of a General Purpose ARM-based Processing Unit for the ATLAS TileCal sROD
The Large Hadron Collider at CERN generates enormous amounts of raw data which present a serious computing challenge. After Phase-II upgrades in 2022, the data output from the ATLAS Tile Calorimeter will increase by 200 times to 41 Tb/s! ARM processors are common in mobile devices due to their low cost, low energy consumption and high performance. It is proposed that a cost-effective, high data throughput Processing Unit (PU) can be developed by using several consumer ARM processors in a cluster configuration to allow aggregated processing performance and data throughput while maintaining minimal software design difficulty for the end-user. This PU could be used for a variety of high-level functions on the high-throughput raw data such as spectral analysis and histograms to detect possible issues in the detector at a low level. High-throughput I/O interfaces are not typical in consumer ARM System on Chips but high data throughput capabilities are feasible via the novel use of PCI-Express as the I/O interface to the ARM processors. An overview of the PU is given and the results for performance and throughput testing of four different ARM Cortex System on Chips are presented